Technical Field of the Invention
This invention relates generally to data communication networks and in particular to Address Resolution Protocol (ARP) forwarding within network devices.
Description of Related Art
Data communication networks allow many different computing devices, for example, personal computers, IP telephony devices and/or servers, to communicate with each other and/or with various other network elements or remote servers attached to the network. For example, data communication networks may include, without limitation, Metro Ethernet or Enterprise Ethernet networks that support multiple applications including, for example, voice-over-IP (VoIP), data and video applications. Such networks regularly include many interconnected nodes, commonly known as switches or routers, for routing traffic through the network.
The various nodes are often distinguished based on their location within particular areas of the network, commonly characterizing two or three “tiers” or “layers,” depending on the size of the network. Conventionally, a three tier network includes an edge layer, an aggregation layer and a core layer (whereas a two tier network includes only an edge layer and core layer). The edge layer of data networks includes edge (also called access) networks that typically provide connectivity from a customer or home network, such as a local area network, to a metro or core network. The edge/access layer is the entry point of the network, i.e., to which the customer network is nominally attached, and the switches residing at the edge layer are known as edge switches. Different types of edge networks include digital subscriber line, hybrid fiber coax (HFC), fiber to the home and various customer networks, such as campus and data center networks. Edge switches may perform, for example, L2 switching functions for the attached devices. The edge switches are generally connected to one or more end devices in the customer network, and also to an aggregation layer that terminates access links coming from multiple edge switches. Switches residing at the aggregation layer are known as aggregation switches. Aggregation switches may perform, for example, L2 switching and L3 routing of traffic received via the aggregate links from the edge switches. The aggregation layer is connected to a metro or core network layer that performs Layer 3/IP routing of traffic received from the aggregation switches (in a three tier network) or from edge switches (in a two tier network). As will be appreciated, nodes at each incremental layer of the network typically have larger capacity and faster throughput.
Recently, there has been an explosion in the number of end devices handled by the switches/routers in data communication networks. This explosion, along with the continued demand for high performance throughput, has motivated administrators to deploy switches with off-the-shelf Application Specific Integrated Circuits (ASICs) that are more cost effective than proprietary ASICs with extended memory support. In general, the switches include a plurality of network interfaces (NIs), each including a routing ASIC. To be able to route traffic at wire-rate, the forwarding must be done by the routing ASIC on the network interface using tables programmed onto the ASIC. One such table is the Address Resolution Protocol (ARP) table, which is used for a direct-match between the destination IP address of the packet and a physical address, such as a Media Access Control (MAC) address.
However, the routing ASIC has fixed sized tables in hardware that can become a limitation in deployments needing more forwarding entries than are available. For example, when the ARP table (and/or related tables, e.g. the next-hop table) is full, the traffic destined for other IP addresses on the local subnet that could not be programmed in hardware gets trapped to the CPU of the network interface, and software performs the routing. This is undesirable as the software cannot achieve very high rates of routing.
Existing solutions have included building more expensive systems with larger on-chip tables or with expanded memory to increase the table size to accommodate every expected host. Nevertheless, the explosion in the number of end devices has resulted in administrators incurring the same problem on different scales over and over again. Adding larger tables to ASICs with expanded memory each time is not cost effective, and is not a viable solution long-term.